Common Options : Enabled, Disabled

Details

This BIOS feature is similar to the Byte Merge feature.

If you have already read about the CPU to PCI Write Buffer feature, you should know that the chipset has an integrated write buffer which allows the CPU to immediately write up to four words of PCI writes to it, thus freeing it quickly and allowing it to work on other tasks.

However, the CPU doesn't always write 32-bit data to the PCI bus. 8-bit and 16-bit writes can also take place. But while the CPU may write 8-bits of data to the PCI bus, it is considered as a single PCI transaction, equivalent to a 16-bit or 32-bit write. This reduces the effective PCI bandwidth, especially if there are many 8-bit or 16-bit CPU-to-PCI writes.

To solve this problem, the write buffer can be programmed to accumulate and merge 8-bit and 16-bit writes into 32-bit writes. The buffer then writes the merged data to the PCI bus. As you can see, merging the smaller 8-bit or 16-bit writes into a few large 32-bit writes reduces the number of PCI transactions required. This increases the efficiency of the PCI bus and improves its bandwidth.

This feature controls the byte merging capability of the PCI write buffer. If it is enabled, every write transaction will go straight to the write buffer. They are accumulated until enough data is available to be written to the PCI bus in a single burst. This improves the PCI bus' performance so it's recommended that you enable this feature.

If you disable PCI Dynamic Bursting, all writes will still go to the PCI write buffer (if CPU to PCI Write Buffer has been enabled). But the buffer won't accumulate and merge the data. The data is written to the PCI bus as soon as it is free. As such, there may be a loss of PCI bus efficiency, particularly when 8-bit or 16-bit data is written to the bus.

Note that like Byte Merge, this feature may not be compatible with certain PCI network interface cards. For more details, please check out the Byte Merge feature.