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Act Bank A to B CMD Delay
Common Options : 2 Cycles, 3 Cycles
Details
The name Act Bank A to B CMD Delay is actually short for
Active Bank A to Active Bank B Command Delay. This feature
controls the delay between successive ACTIVE commands to different
memory banks (tRRD). The shorter the delay, the faster
the next bank can be activated for read or write operations.
Therefore, it's recommended that you use the lower value of 2
cycles for a shorter delay between bank activations and
consequently, higher DRAM performance. However, not all DRAM modules
can work properly with the lower value of 2 cycles and may exhibit
stability problems. When that happens, just revert back to the 3
cycles.
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