Most processors come with two level of caches. The first level is integrated within the processor core itself and is thus the fastest. Data stored there can be used by the processor at no cost in clock cycles at all. The next level of cache, called L2 or secondary cache, is situated outside the core and usually runs at a lower clockspeed than the core though it may also run as fast as the core itself. However, even if it runs at the same clockspeed as the core, it will be slower than the L1 or primary cache because it's not part of the core itself.

In this article, we will be looking at the L2 or secondary cache. It's situated outside the core, either within the same package or in a separate package. So, its throughput will be lower than the L1 or primary cache's. However, the size of the L2 cache is always much larger than the L1 cache and if it runs fast enough, its throughput can come close to that of the L1 cache. So, the L2 cache plays a very important role in maintaining the high memory throughput to the processor.

Recently, many manufacturers have included a BIOS option that enables the user to control the latency of the L2 cache. An excellent example would be ABIT's SoftMenu II and SoftMenu III (shown below).

There are 16 different values available under the Level 2 Cache Latency option, with L2 cache latency values of 1 to 15 and a default value which reverts to the processor's default L2 cache latency. Note, however, that ABIT maintains that this BIOS function only works for older Celerons and Pentium II processors that are based on the 0.25μ process. The newer Celerons and Pentium !!! processors (based on the 0.18μ process) are not affected by this function.

As far as latency is concerned, the lower the value, the less delay occurs and the higher the performance. However, don't immediately set the value of 1 for Level 2 Cache Latency. According to ABIT, if you set a value that's too low, the L2 cache will cease to work though the processor and L1 cache will still continue to work. That means the system will continue to run, only with a lower performance.

However, as far as my experience goes, if the L2 cache latency is set too low, the L2 cache will fail and the system will crash. It won't allow the processor and L1 cache to continue working. Anyway, either way, this means you will have to test how low a latency your processor's L2 cache can really support. That means working down the L2 cache latency values one by one and stressing the processor (which stress the L2 cache also) each time to ensure it will work with such a latency.