Processors run many, many times faster than RAM. Take, for example, the Intel Celeron 500 and PC100 SDRAM. At 500MHz, each CPU clock cycle takes only 2ns. On the other hand, the initial data fetch from the PC100 SDRAM requires 20-30ns and later 10ns for the following subsequent data fetches. That means there's a minimum of 5 CPU clock cycles between each SDRAM cycle. Needless to say, the performance of the processor would deteriorate tremendously as the processor will have to wait several cycles for the next piece of data after processing the previous piece.

Faster RAM would naturally be the answer to the problem. But even the fastest SDRAM cannot run as fast as the processor core. Therefore, designers turn to SRAMs which can run very fast but are horrendously expensive. So, there's no way SRAMs can be used to replace SDRAM or older RAM technologies like EDO DRAM and DRAM.

The designers compromised instead, attempting to obtain the performance of SRAM without its prohibitive cost. They settled for using a small amount of SRAM to act as a buffer between the processor and the RAM. This fast RAM buffer (called cache) was designed to store the recently read or prefetched data from the RAM.

So, when the processor needs data, it first looks into the cache. If the data it needs can be found there, it can retrieve that data with little or no delay. Only if the data isn't there does the processor need to look into the slower RAM. Most of the time, however, the cache is able to fulfill the processor's data requests so the effect of the slower RAM on the processor is greatly reduced. The system's memory bandwidth is greatly increased and the processor is now able to run much more efficiently.