Options : 7.8 μsec, 15.6 μsec, 31.2 μsec, 64 μsec, 128 μsec

Memory cells normally need to be refreshed every 64 msec. However, simultaneously refreshing all rows in a typical memory chip will cause a big surge in power requirements. In addition, a simultaneous refresh causes all data requests to stall, which impacts performance.

To avoid both problems, refreshes are normally staggered according to the number of rows. Since a typical memory chip contains 4096 rows, the memory controller usually refreshes a different row every 15.6 μsec (64,000 μsec / 4096 rows = 15.6 μsec). This reduces the amount of current used during the refreshes and data can still be accessed from the other rows.

Usually, DIMMs that use 128Mbit or smaller memory chips have 4096 rows while memory chips with higher capacity (256Mbit and above) will have 8192 rows. For memory chips that come with 8192 rows, the refresh interval will need to be halved to 7.8 μsec because there are now twice as many rows to serviced within the stipulated 64 msec for the entire chip.

Therefore, the typical refresh interval for 128Mbit (not MB!) or smaller memory chips would be 15.6 μsec while those for 256Mbit or larger memory chips would be 7.8 μsec. Note that if you are using a mix of 128Mbit or smaller DIMMs with 256Mbit or larger DIMMs, the fail-safe Refresh Interval would be 7.8 μsec, not 15.6 μsec.

Although the JEDEC standards call for a 64 msec refresh cycle, memory chips these days can hold data for longer than that. So, using a longer refresh cycle is quite possible. With a longer refresh cycle, the memory chips are refreshed less often, reducing both the amount of bandwidth wasted on refreshes and the amount of power consumed (which is great for laptops and other portable devices).

For better performance, you should consider increasing the Refresh Interval. You can try increasing the Refresh Interval from the default values (15.6 μsec for 128Mbit or smaller memory chips and 7.8 μsec for 256Mbit or larger memory chips) up to 128 μsec. Note that if you increase the Refresh Interval too much, the memory cells may lose their contents.

Therefore, you should start with small increases in the Refresh Interval and test your system after each hike before increasing it further. If you face stability problems upon increasing the Refresh Interval, reduce the Refresh Interval step by step until the system is stable.

Options : 7.8 μsec, 15.6 μsec, 64 μsec

This BIOS feature is similar to the Refresh Interval option.

Options : Disabled, 0 Cycle, 8 Cycles, 12 Cycles, 16 Cycles, 24 Cycles, 32 Cycles, 48 Cycles

This feature sets the number of idle cycles the SDRAM bank has to wait before recharging. This allows you to improve the efficiency of the SDRAM read and write cycles by adjusting the amount of time that the bank is allowed to remain idle before it's recharged.

Increasing the SDRAM Idle Limit to more than the default of 8 cycles allows the SDRAM bank to delay recharging longer during times of no activity so that if a read/write command comes along, it can be instantly satisfied.

However, this is limited by the refresh cycle already set by the BIOS. That means the SDRAM bank will refresh when it needs to be recharged whether the number of idle cycles have reached the SDRAM Idle Limit or not. So, the SDRAM Idle Limit setting can only be used to force the refreshing of the SDRAM bank before the set refresh cycle but not to actually delay the refresh cycle.

Reducing the number of cycles from the default of 8 cycles to 0 cycles means that the SDRAM bank will immediately refresh once no valid requests are sent to the memory controller. This may increase the efficiency of the SDRAM by refreshing the bank when it's idle. It can be seen as masking the effects of refreshing by doing it during idle cycles. But if there are any data requests after the bank starts its refresh cycle, they will have to wait till the bank is completely refreshed and activated before they can be satisfied.

Because refreshes do not occur that often (at only about every 64 msec), the impact of refreshing on SDRAM performance is really quite minimal and the benefits of masking the SDRAM's refreshes during idle cycles will not be noticeable. In fact, there's a high risk that data requests will get stalled more often, especially with the idle limit of 0. On the plus side, data in the SDRAM will be refreshed more often and there will be less chance of losing data due to insufficiently refreshed memory cells.

So, if you want to keep your data refreshed more often with a possibility of slightly better SDRAM performance, keep the SDRAM Idle Limit at 8 cycles. Setting it to 0 cycles refreshes the SDRAM too often and greatly increases the risk of stalling data requests.

But for best performance, this feature should be disabled so that refreshing can be delayed for as long as possible. However, if your motherboard's BIOS come with a Refresh Interval feature, you can use this feature to boost the reliability of data in the memory cells if you have greatly increased the Refresh Interval.

As increasing the Refresh Interval to high values like 64 of 128 μsec may cause memory cells to fail to retain their data, setting a low SDRAM Idle Limit allows the memory cells to be refreshed more often, with a high chance of those refreshes being done during idle cycles. This combines the best of both worlds - long refresh interval when the memory controller is being stressed and more refreshes when the memory controller is idle.

Options : 0 Cycle, 1 Cycle

This feature determines how long the memory controller should wait before sending the read data to the data requester (i.e. CPU, graphics card, etc..). By default, a wait state is added before the data is sent to the requester. Therefore, read performance is reduced because the memory controller has to wait one cycle before sending the data.

For optimal performance, you should set the Read Wait State to 0 Cycle. Note that this may cause system instabilities in certain situations. When that happens, just reset the value to 1 Cycle.