Options : Enabled, Disabled

This BIOS option controls the PCI write buffer. If this is enabled, then every write transaction on the PCI bus goes straight to the write buffer. Burst transactions are then sent on their way as soon as there are enough to send in a single burst.

If this option is disabled, the data will go to the write buffer and burst-transferred later (when the PCI bus is free or when the buffer is full) if the write transaction is a burst transaction. If the write transaction is not a burst transaction, then the write buffer is flushed and the data is written to the PCI bus immediately.

It is recommended that you enable PCI Dynamic Bursting for better PCI performance.

PCI Master 0 WS Write

Options : Enabled, Disabled

This function determines whether there's a delay before any writes to the PCI bus. If this is enabled, then writes to the PCI bus are executed immediately (with zero wait states), as soon as the PCI bus is ready to receive data. But if it is disabled, then every write transaction to the PCI bus is delayed by one wait state.

Normally, it's recommended that you enable this for faster PCI performance. However, disabling it may be useful when overclocking the PCI bus results in instability. The delay will generally improve the overclockability of the PCI bus. 

PCI Delay Transaction

Options : Enabled, Disabled

This feature is similar to the Delayed Transaction BIOS option. It is used to meet the latency of PCI cycles to and from the ISA bus. The ISA bus is much, much slower than the PCI bus. Thus, PCI cycles to and from the ISA bus take a longer time to complete and this slows the PCI bus down.

However, enabling Delayed Transaction enables the chipset's embedded 32-bit posted write buffer to support delayed transaction cycles. This means that transactions to and from the ISA bus are buffered and the PCI bus can be freed to perform other transactions while the ISA transaction is underway.

This option should be enabled for better performance and to meet PCI 2.1 specifications. Disable it only if your PCI cards cannot work properly or if you are using an ISA card that is not PCI 2.1 compliant.

PCI#2 Access #1 Retry

Options : Enabled, Disabled

This BIOS feature is linked to the CPU to PCI Write Buffer. Normally, the CPU to PCI Write Buffer is enabled. All writes to the PCI bus are, as such, immediately written into the buffer, instead of the PCI bus. This frees up the CPU from waiting till the PCI bus is free. The data are then written to the PCI bus when the next PCI bus cycle starts.

There's a possibility that the buffer write to the PCI bus may fail. When that happens, this BIOS option determines if the buffer write should be reattempted or sent back for arbitration. If this BIOS option is enabled, then the buffer will attempt to write to the PCI bus until successful. If disabled, the buffer will flush its contents and register the transaction as failed. The CPU will have to write again to the write buffer.

It is recommended that you enable this feature unless you have many slow PCI devices in your system. In that case, disabling this feature will prevent the generation of too many retries which may severely tax the PCI bus.

Master Priority Rotation

Options : 1 PCI, 2 PCI, 3 PCI

This feature controls the CPU's access to the PCI bus.

If you choose 1 PCI, the CPU will always be granted access right after the current PCI bus master transaction completes, irrespective of how many other PCI bus masters are on the queue. This affords the quickest CPU access to the PCI bus but means poorer performance for the PCI bus devices.

If you choose 2 PCI, the CPU will be granted access after the current and the next PCI transaction completes. In other words, the CPU is guaranteed access after two PCI bus master transactions, irrespective of how many other PCI bus masters are also on the queue. This means the CPU has to wait a little longer than with the 1 PCI option but PCI devices will have quicker access to the PCI bus.

If you choose 3 PCI, the CPU will only be granted access to the PCI bus after the current PCI bus master transaction and the following two PCI bus master transactions on the queue have been completed. So, the CPU has to wait for three PCI bus masters to complete their transactions on the PCI bus before it can gain access to the PCI bus itself. This means poorer CPU-to-PCI performance but PCI bus master devices will enjoy better performance.

But irrespective of your choice, the CPU is guaranteed access to the PCI bus after a maximum of 3 PCI master grants. It doesn't matter if there are numerous PCI bus masters on the queue or when the CPU requested access to the PCI bus. It will always be granted access after one PCI bus master transaction (1 PCI), two transactions (2 PCI) or three transactions (3 PCI).

AGP 4X Mode

Options : Enabled, Disabled

This feature is only found on motherboards that support AGP4X. However, it's usually set to Disabled by default because not everyone will be using an AGP4X card with the motherboard. For users of AGP1X or 2X cards, this BIOS option needs to be disabled for the cards to work properly. In order to prevent complications, manufacturers prefer to just disable AGP4X mode. 

However, this means users of AGP4X cards will lose out on the greater bandwidth afforded by the AGP4X mode. While AGP4X mode's actual transfer rate isn't significantly higher than that of AGP2X, it's still a waste not to use the mode when it's available.

So, if you own an AGP4X card, it's recommended that you enable AGP4X mode for better AGP performance. Leave it as disabled only if you have a graphics card that can only support AGP1X or AGP2X transfer modes.